diff -ur uc-origs/uClinux-2.4.27-uc1/arch/armnommu/kernel/entry-armv.S uClinux-2.4.27-uc1/arch/armnommu/kernel/entry-armv.S --- uc-origs/uClinux-2.4.27-uc1/arch/armnommu/kernel/entry-armv.S 2004-12-12 21:48:45.000000000 +0100 +++ uClinux-2.4.27-uc1/arch/armnommu/kernel/entry-armv.S 2005-01-21 17:26:34.000000000 +0100 @@ -1743,9 +1743,50 @@ * other mode than FIQ... Ok you can switch to another mode, but you can't * get out of that mode without clobbering one register. */ +#ifndef CONFIG_ARCH_CX821XX ENTRY(vector_FIQ) disable_fiq subs pc, lr, #4 +#else +/******************************************************************************* +/ Function: vector_FIQ +/ Description: Handles fast interrupt exception, +/ +/ Inputs Working Outputs +/ R0 = NA R0 = R0 = Restored +/ R1 = NA R1 = R1 = Restored +/ R2 = NA R2 = R2 = Restored +/ R3 = NA R3 = R3 = Restored +/ R4 = NA R4 = R4 = Restored +/ R5 = NA R5 = R5 = Restored +/ R6 = NA R6 = R6 = Restored +/ R7 = NA R7 = R7 = Restored +/ R8 = NA R8 = R8 = Restored +/ R9 = NA R9 = R9 = Restored +/ R10 = NA R10 = R10 = Restored +/ R11 = NA R11 = R11 = Restored +/ R12 = NA R12 = R12 = Restored +/ +/ This routine is entered with r8-r14 (r8-r12, SP and LR) replaced by r8_fiq - +/ r14_fiq. The CPSR will have been copied to the SPSR_fiq. +/*******************************************************************************/ +vector_FIQ: + /* + Adjust return address in LR now since we we return via restoring all regs + including the LR, but the LR is restored to the PC (R15). + */ + sub lr, lr, #4 + + @ Save registers + stmfd sp!, {r0-r7, lr} + +#if 0 + @ call the FIQ handler + bl cnxt_do_FIQ +#endif + @ Restore registers and return (The "^" causes the CPSR to be restored from the SPSR) + ldmfd sp!, {r0-r7, pc}^ +#endif /*============================================================================= * Address exception handler diff -ur uc-origs/uClinux-2.4.27-uc1/arch/armnommu/kernel/head-armv.S uClinux-2.4.27-uc1/arch/armnommu/kernel/head-armv.S --- uc-origs/uClinux-2.4.27-uc1/arch/armnommu/kernel/head-armv.S 2004-12-12 21:48:45.000000000 +0100 +++ uClinux-2.4.27-uc1/arch/armnommu/kernel/head-armv.S 2005-01-21 17:26:34.000000000 +0100 @@ -209,6 +209,9 @@ #elif defined(CONFIG_BOARD_S3C2500REFRGP) mov r1, #MACH_TYPE_S3C2500REFRGP #endif + mov r0, # F_BIT | I_BIT | FIQ_MODE + msr cpsr_c, r0 @ Put us in FIRQ mode and turn interrupts off + ldr r13, =_firq_stack_bottom @ initialize FIRQ stack ptr mov r0, #F_BIT | I_BIT | MODE_SVC @ make sure svc mode msr cpsr_c, r0 @ and all irqs disabled @@ -876,3 +858,9 @@ #endif #endif + .section .stack, "w" + +_firq_stack: +_firq_stack_top: + .space 512 +_firq_stack_bottom: diff -ur uc-origs/uClinux-2.4.27-uc1/arch/armnommu/mm/proc-arm940.S uClinux-2.4.27-uc1/arch/armnommu/mm/proc-arm940.S --- uc-origs/uClinux-2.4.27-uc1/arch/armnommu/mm/proc-arm940.S 2004-12-12 21:48:45.000000000 +0100 +++ uClinux-2.4.27-uc1/arch/armnommu/mm/proc-arm940.S 2005-01-21 17:26:34.000000000 +0100 @@ -22,8 +22,8 @@ /* * the cache line size of the I and D cache */ -#define DCACHELINESIZE 32 -#define ICACHELINESIZE 32 +#define DCACHELINESIZE 16 +#define ICACHELINESIZE 16 /* * and the page size @@ -136,19 +136,21 @@ * Re-written to use Index Ops. * Uses registers r1, r3 and ip */ - mov r1, #7 << 5 @ 8 segments + mov r1, #4 << 4 @ 4 segments 1: orr r3, r1, #63 << 26 @ 64 entries 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index subs r3, r3, #1 << 26 bcs 2b @ entries 63 to 0 - subs r1, r1, #1 << 5 - bcs 1b @ segments 7 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 3 to 0 #endif teq r2, #0 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c10, 4 @ drain WB mov pc, lr +cpu_arm940_cache_clean_invalidate_all_string: + .asciz "cpu_arm940_cache_clean_invalidate_all\n" /* * cpu_arm940_cache_clean_invalidate_range(start, end, flags) * @@ -157,23 +159,13 @@ * start: Area start address * end: Area end address * flags: nonzero for I cache as well + * + * With ARM 940T, we cannot determine which lines are associated with which + * memory range. Therefore we clean and invalidate all. */ .align 5 ENTRY(cpu_arm940_cache_clean_invalidate_range) - bic r0, r0, #DCACHELINESIZE - 1 @ && added by PGM - sub r3, r1, r0 - cmp r3, #MAX_AREA_SIZE - bgt cpu_arm940_cache_clean_invalidate_all_r2 -1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry - add r0, r0, #DCACHELINESIZE - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry - add r0, r0, #DCACHELINESIZE - cmp r0, r1 - blt 1b - teq r2, #0 - movne r0, #0 - mcrne p15, 0, r0, c7, c5, 0 @ invalidate I cache - mov pc, lr + b cpu_arm940_cache_clean_invalidate_all_r2 /* * cpu_arm940_flush_ram_page(page) @@ -181,10 +173,14 @@ * clean and invalidate all cache lines associated with this area of memory * * page: page to clean and invalidate + * + * With ARM 940T, we cannot determine which lines are associated with which + * pages. Therefore we clean and invalidate all. */ .align 5 ENTRY(cpu_arm940_flush_ram_page) - mov pc, lr + sub r2, r2, r2 + b cpu_arm940_cache_clean_invalidate_all /* ================================ D-CACHE =============================== */ @@ -197,21 +193,16 @@ * around the boundaries if the start and/or end address are not cache * aligned. * + * With ARM 940T, we cannot determine which lines are associated with which + * pages. Therefore we clean and invalidate all. + * * start: virtual start address * end: virtual end address */ .align 5 ENTRY(cpu_arm940_dcache_invalidate_range) - tst r0, #DCACHELINESIZE - 1 - bic r0, r0, #DCACHELINESIZE - 1 - mcrne p15, 0, r0, c7, c10, 1 @ clean D entry - tst r1, #DCACHELINESIZE - 1 - mcrne p15, 0, r1, c7, c10, 1 @ clean D entry -1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry - add r0, r0, #DCACHELINESIZE - cmp r0, r1 - blt 1b - mov pc, lr + sub r2, r2, r2 + b cpu_arm940_cache_clean_invalidate_all /* * cpu_arm940_dcache_clean_range(start, end) @@ -220,26 +211,35 @@ * clean data, such that peripheral accesses to the physical RAM fetch * correct data. * + * With ARM 940T, we cannot determine which lines are associated with which + * range. Therefore we clean all DCache. + * * start: virtual start address * end: virtual end address */ .align 5 +cpu_arm940_dcache_clean_all: ENTRY(cpu_arm940_dcache_clean_range) - bic r0, r0, #DCACHELINESIZE - 1 - sub r1, r1, r0 - cmp r1, #MAX_AREA_SIZE - mov r2, #0 - bgt cpu_arm940_cache_clean_invalidate_all_r2 - -1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #DCACHELINESIZE - mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #DCACHELINESIZE - subs r1, r1, #2 * DCACHELINESIZE - bpl 1b - mcr p15, 0, r2, c7, c10, 4 @ drain WB + mov ip, #0 +#ifdef CONFIG_CPU_ARM940_FORCE_WRITE_THROUGH +#else +/* + * 'Clean whole DCache' + * Uses registers r1, r3 and ip + */ + mov r1, #4 << 4 @ 4 segments +1: orr r3, r1, #63 << 26 @ 64 entries +2: mcr p15, 0, r3, c7, c10, 2 @ clean D index + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 3 to 0 +#endif + mcr p15, 0, ip, c7, c10, 4 @ drain WB mov pc, lr +cpu_arm940_dcache_clean_all_string: + .asciz "cpu_arm940_dcache_clean_all\n" /* * cpu_arm940_dcache_clean_page(page) * @@ -248,23 +248,13 @@ * * page: virtual address of page to clean from dcache * - * Note: - * 1. we don't need to flush the write buffer in this case. - * 2. we don't invalidate the entries since when we write the page - * out to disk, the entries may get reloaded into the cache. + * With ARM 940T, we cannot determine which lines are associated with which + * page. Therefore we clean all DCache. + * */ .align 5 ENTRY(cpu_arm940_dcache_clean_page) -#ifndef CONFIG_CPU_ARM940_FORCE_WRITE_THROUGH - mov r1, #PAGESIZE -1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #DCACHELINESIZE - mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #DCACHELINESIZE - subs r1, r1, #2 * DCACHELINESIZE - bne 1b -#endif - mov pc, lr + b cpu_arm940_dcache_clean_all /* * cpu_arm940_dcache_clean_entry(addr) @@ -272,15 +262,14 @@ * Clean the specified entry of any caches such that the MMU * translation fetches will obtain correct data. * + * With ARM 940T, we cannot determine which lines are associated with which + * page. Therefore we clean all DCache. + * * addr: cache-unaligned virtual address */ .align 5 ENTRY(cpu_arm940_dcache_clean_entry) -#ifndef CONFIG_CPU_ARM940_FORCE_WRITE_THROUGH - mcr p15, 0, r0, c7, c10, 1 @ clean D entry -#endif - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mov pc, lr + b cpu_arm940_dcache_clean_all /* ================================ I-CACHE =============================== */ @@ -289,20 +278,18 @@ * * invalidate a range of virtual addresses from the Icache * + * With ARM 940T, we cannot determine which lines are associated with which + * page/range. Therefore we invalidate all ICache. Since this routine must + * also synchronize the I and D cache, we must flush the D cache + * * start: virtual start address * end: virtual end address */ .align 5 ENTRY(cpu_arm940_icache_invalidate_range) -1: mcr p15, 0, r0, c7, c10, 1 @ Clean D entry - add r0, r0, #DCACHELINESIZE - cmp r0, r1 - blo 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 @ drain WB ENTRY(cpu_arm940_icache_invalidate_page) - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mov pc, lr + mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache + b cpu_arm940_dcache_clean_all /* ================================== TLB ================================= */ @@ -402,25 +389,6 @@ __arm940_setup: MRC p15, 0, R0, c1, c0, 0 @ get control register - -/* - * Clear out 'unwanted' bits (then put them in if we need them) - */ - bic r0, r0, #0x0e00 @ ....??r......... - bic r0, r0, #0x0002 @ ..............a. - bic r0, r0, #0x000c @ W,D - bic r0, r0, #0x1000 @ I -/* - * Turn on what we want - */ - orr r0, r0, #0x0001 @ Enable PU - -#ifdef CONFIG_CPU_ARM940_D_CACHE_ON - orr r0, r0, #0x0004 @ Enable D cache -#endif -#ifdef CONFIG_CPU_ARM940_I_CACHE_ON - orr r0, r0, #0x1000 @ I Cache on -#endif mov pc, lr .text