diff -ur uClinux-2.4.6.0pre1/arch/armnommu/Makefile uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/Makefile --- uClinux-2.4.6.0pre1/arch/armnommu/Makefile 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/Makefile 2005-01-04 13:24:48.000000000 +0100 @@ -7,7 +7,8 @@ # # Copyright (C) 1995-2001 by Russell King -LINKFLAGS :=-p -X -T arch/armnommu/vmlinux.lds +#LINKFLAGS :=-p -X -T arch/armnommu/vmlinux.lds +LINKFLAGS :=-p -X GZFLAGS :=-9 CFLAGS +=-fno-common -pipe -fno-builtin -D__linux__ @@ -56,7 +57,7 @@ ifeq ($(CONFIG_CPU_32),y) PROCESSOR = armv -TEXTADDR = 0xC0008000 +TEXTADDR = 0x0 endif ifeq ($(CONFIG_ARCH_ARCA5K),y) @@ -130,6 +131,13 @@ CFLAGS += -DNO_MM -DMAGIC_ROM_PTR endif +ifeq ($(CONFIG_ARCH_CX821XX),y) +MACHINE = cx821xx +TEXTADDR = 0x800000 +CFLAGS += -DNO_MM -DMAGIC_ROM_PTR +LINKFLAGS += -T arch/armnommu/mach-$(MACHINE)/ramlinux.lds +endif + ifeq ($(CONFIG_ARCH_SPIPE),y) TEXTADDR = 0x808000 MACHINE = spipe @@ -249,6 +257,9 @@ @true endif +linux.bin: linux + $(CROSS_COMPILE)objcopy -O binary linux linux.bin + # My testing targets (that short circuit a few dependencies) zImg:; @$(MAKEBOOT) zImage Img:; @$(MAKEBOOT) Image diff -ur uClinux-2.4.6.0pre1/arch/armnommu/config.in uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/config.in --- uClinux-2.4.6.0pre1/arch/armnommu/config.in 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/config.in 2005-01-04 18:01:02.000000000 +0100 @@ -49,43 +49,77 @@ if [ "$CONFIG_ARCH_CNXT" = "y" ]; then choice ' Conexant/Mindspeed architecture' \ " P52xxCtrl CONFIG_ARCH_P52 \ - sp_CN9414 CONFIG_ARCH_SPIPE" P52xxCtrl + sp_CN9414 CONFIG_ARCH_SPIPE \ + CX821xxCtrl CONFIG_ARCH_CX821XX" CX821xxCtrl if [ "$CONFIG_ARCH_P52" = "y" ]; then choice ' P52xx board implementation' \ "IAD_EVM CONFIG_IAD_EVM \ JSCHornet CONFIG_HORNET" IAD_EVM fi + + choice ' Board Support Package' " \ + HASBANI CONFIG_BD_HASBANI \ + GOLDENGATE CONFIG_BD_GOLDENGATE \ + MACKINAC CONFIG_BD_MACKINAC \ + RUSHMORE CONFIG_BD_RUSHMORE \ + OAKLAND CONFIG_BD_OAKLAND \ + LIONSGATE CONFIG_BD_LIONSGATE \ + " MACKINAC + + if [ "$CONFIG_BD_HASBANI" = "y" ]; then + define_bool CONFIG_CHIP_P52 y + fi + if [ "$CONFIG_BD_GOLDENGATE" = "y" ]; then + define_bool CONFIG_CHIP_CX82100 y + define_bool CONFIG_CHIP_CX82110 n + fi + if [ "$CONFIG_BD_MACKINAC" = "y" ]; then + define_bool CONFIG_CHIP_CX82110 y + define_bool CONFIG_CHIP_CX82100 n + fi + if [ "$CONFIG_BD_RUSHMORE" = "y" ]; then + define_bool CONFIG_CHIP_CX82110 y + define_bool CONFIG_CHIP_CX82100 n + fi + if [ "$CONFIG_BD_OAKLAND" = "y" ]; then + define_bool CONFIG_CHIP_CX82100 y + define_bool CONFIG_CHIP_CX82110 n + fi + if [ "$CONFIG_BD_LIONSGATE" = "y" ]; then + define_bool CONFIG_CHIP_CX82100 y + define_bool CONFIG_CHIP_CX82110 n + fi fi # ARM940T -if [ "$CONFIG_ARCH_CNXT" = "y" ]; then - define_bool CONFIG_CPU_32 y - define_bool CONFIG_CPU_26 n - define_bool CONFIG_CPU_ARM940T y - define_bool CONFIG_NO_PGT_CACHE y -bool 'Set flash/sdram size and base addr' CONFIG_SET_MEM_PARAM - -if [ "$CONFIG_SET_MEM_PARAM" = "y" ]; then - hex 'SDRAM Base Address' DRAM_BASE 0x00800000 - hex 'SDRAM Size ' DRAM_SIZE 0x00800000 - hex 'FLASH Base Address ' FLASH_MEM_BASE 0x00400000 - hex 'FLASH Size ' FLASH_SIZE 0x00400000 -fi - -if [ "$CONFIG_SET_MEM_PARAM" = "n" ]; then - define_hex DRAM_BASE 0x00800000 - define_hex DRAM_SIZE 0x00800000 - define_hex FLASH_MEM_BASE 0x00400000 - define_hex FLASH_SIZE 0x00400000 -fi - - bool ' ARM940T CPU idle' CONFIG_CPU_ARM940_CPU_IDLE - bool ' ARM940T I-Cache on' CONFIG_CPU_ARM940_I_CACHE_ON - bool ' ARM940T D-Cache on' CONFIG_CPU_ARM940_D_CACHE_ON -if [ "$CONFIG_CPU_ARM940_D_CACHE_ON" = "y" ] ; then - bool ' Force write through caches on ARM940T' CONFIG_CPU_ARM940_WRITETHROUGH -fi +if [ "$CONFIG_CHIP_CX82100" = "y" -o "$CONFIG_CHIP_CX82110" = "y" ]; then + define_bool CONFIG_CPU_32 y + define_bool CONFIG_CPU_26 n + define_bool CONFIG_CPU_ARM940T y + define_bool CONFIG_NO_PGT_CACHE y + bool 'Set flash/sdram size and base addr' CONFIG_SET_MEM_PARAM + + if [ "$CONFIG_SET_MEM_PARAM" = "y" ]; then + hex 'SDRAM Base Address' DRAM_BASE 0x00800000 + hex 'SDRAM Size ' DRAM_SIZE 0x00780000 + hex 'FLASH Base Address ' FLASH_MEM_BASE 0x00400000 + hex 'FLASH Size ' FLASH_SIZE 0x00400000 + fi + + if [ "$CONFIG_SET_MEM_PARAM" = "n" ]; then + define_hex DRAM_BASE 0x00800000 + define_hex DRAM_SIZE 0x00780000 + define_hex FLASH_MEM_BASE 0x00400000 + define_hex FLASH_SIZE 0x00400000 + fi + + bool ' ARM940T CPU idle' CONFIG_CPU_ARM940_CPU_IDLE + bool ' ARM940T I-Cache on' CONFIG_CPU_ARM940_I_CACHE_ON + bool ' ARM940T D-Cache on' CONFIG_CPU_ARM940_D_CACHE_ON + if [ "$CONFIG_CPU_ARM940_D_CACHE_ON" = "y" ] ; then + bool ' Force write through caches on ARM940T' CONFIG_CPU_ARM940_WRITETHROUGH + fi fi @@ -136,7 +170,11 @@ fi fi +choice 'Kernel executes from' \ + "RAM CONFIG_RAMKERNEL \ + ROM CONFIG_ROMKERNEL" RAM +bool ' Use uCbootstrap calls' CONFIG_UCBOOTSTRAP endmenu @@ -160,8 +198,11 @@ tristate 'NWFPE math emulation' CONFIG_NWFPE choice 'Kernel core (/proc/kcore) format' \ "ELF CONFIG_KCORE_ELF \ - A.OUT CONFIG_KCORE_AOUT" ELF -define_bool CONFIG_BINFMT_FLAT y + A.OUT CONFIG_KCORE_AOUT" A.OUT +tristate 'Kernel support for flat binaries' CONFIG_BINFMT_FLAT +if [ "$CONFIG_BINFMT_FLAT" != "n" ]; then + bool ' Enable ZFLAT support' CONFIG_BINFMT_ZFLAT +fi define_bool CONFIG_KERNEL_ELF y if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then @@ -282,8 +323,11 @@ mainmenu_option next_comment comment 'Kernel hacking' -define_bool CONFIG_FRAME_POINTER y bool 'Find REVISITS' CONFIG_REVISIT +bool 'Config frame pointer' CONFIG_FRAME_POINTER +if [ "$CONFIG_FRAME_POINTER" = "n" ]; then + define_bool CONFIG_NO_FRAME_POINTER y +fi bool 'Verbose kernel error messages' CONFIG_DEBUG_ERRORS bool 'Verbose user fault messages' CONFIG_DEBUG_USER bool 'Include debugging information in kernel binary' CONFIG_DEBUG_INFO diff -ur uClinux-2.4.6.0pre1/arch/armnommu/kernel/armksyms.c uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/armksyms.c --- uClinux-2.4.6.0pre1/arch/armnommu/kernel/armksyms.c 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/armksyms.c 2005-01-04 13:22:41.000000000 +0100 @@ -121,6 +121,9 @@ EXPORT_SYMBOL(pm_idle); EXPORT_SYMBOL(pm_power_off); +extern void __do_softirq(void); +EXPORT_SYMBOL_NOVERS(__do_softirq); + /* processor dependencies */ EXPORT_SYMBOL(__machine_arch_type); diff -ur uClinux-2.4.6.0pre1/arch/armnommu/kernel/entry-armv.S uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/entry-armv.S --- uClinux-2.4.6.0pre1/arch/armnommu/kernel/entry-armv.S 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/entry-armv.S 2005-01-04 17:44:10.000000000 +0100 @@ -644,6 +644,115 @@ #endif +#ifdef CONFIG_ARCH_CX821XX + + ldr r4, =CNXT_INT_STATUS_M + ldr \irqstat, [r4] + + tst \irqstat, #CNXT_INT_MASK_DMA1 + movne \irqnr, #CNXT_INT_LVL_DMA1 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_DMA3 + movne \irqnr, #CNXT_INT_LVL_DMA3 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_DMA2 + movne \irqnr, #CNXT_INT_LVL_DMA2 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_DMA4 + movne \irqnr, #CNXT_INT_LVL_DMA4 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_E1_ERR + movne \irqnr, #CNXT_INT_LVL_E1_ERR + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_E2_ERR + movne \irqnr, #CNXT_INT_LVL_E2_ERR + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_TIMER_1 + movne \irqnr, #CNXT_INT_LVL_TIMER_1 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_TIMER_2 + movne \irqnr, #CNXT_INT_LVL_TIMER_2 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_TIMER_3 + movne \irqnr, #CNXT_INT_LVL_TIMER_3 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_TIMER_4 + movne \irqnr, #CNXT_INT_LVL_TIMER_4 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_USB + movne \irqnr, #CNXT_INT_LVL_USB + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_HOST + movne \irqnr, #CNXT_INT_LVL_HOST + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_HOST_ERR + movne \irqnr, #CNXT_INT_LVL_HOST_ERR + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_DMA8 + movne \irqnr, #CNXT_INT_LVL_DMA8 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_DMA6 + movne \irqnr, #CNXT_INT_LVL_DMA6 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_DMA5 + movne \irqnr, #CNXT_INT_LVL_DMA5 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_DMA_ERR + movne \irqnr, #CNXT_INT_LVL_DMA_ERR + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_DSL + movne \irqnr, #CNXT_INT_LVL_DSL + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_GPIO + movne \irqnr, #CNXT_INT_LVL_GPIO + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_COMMTX + movne \irqnr, #CNXT_INT_LVL_COMMTX + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_COMMRX + movne \irqnr, #CNXT_INT_LVL_COMMRX + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_SW1 + movne \irqnr, #CNXT_INT_LVL_SW1 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_SW2 + movne \irqnr, #CNXT_INT_LVL_SW2 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_SW3 + movne \irqnr, #CNXT_INT_LVL_SW3 + bne 1001f + + tst \irqstat, #CNXT_INT_MASK_SW4 + movne \irqnr, #CNXT_INT_LVL_SW4 + + +1001: +#endif + + #ifdef CONFIG_ARCH_SPIPE @ @ not been tested @@ -1054,6 +1163,47 @@ .align 5 __stubs_start: /* + * Undef instr entry dispatcher - dispatches it to the correct handler for the processor mode + * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC + */ +vector_undefinstr: + @ + @ save mode specific registers + @ + ldr r13, .LCsund + str lr, [r13] @ save lr_UND + mrs lr, spsr + str lr, [r13, #4] @ save spsr_UND + @ + @ now branch to the relevent MODE handling routine + @ + mov r13, #I_BIT | MODE_SVC + msr spsr_c, r13 @ switch to SVC_32 mode + + and lr, lr, #15 + ldr lr, [pc, lr, lsl #2] + movs pc, lr @ Changes mode and branches + +.LCtab_und: .word __und_usr @ 0 (USR_26 / USR_32) + .word __und_invalid @ 1 (FIQ_26 / FIQ_32) + .word __und_invalid @ 2 (IRQ_26 / IRQ_32) + .word __und_svc @ 3 (SVC_26 / SVC_32) + .word __und_invalid @ 4 + .word __und_invalid @ 5 + .word __und_invalid @ 6 + .word __und_invalid @ 7 + .word __und_invalid @ 8 + .word __und_invalid @ 9 + .word __und_invalid @ a + .word __und_invalid @ b + .word __und_invalid @ c + .word __und_invalid @ d + .word __und_invalid @ e + .word __und_invalid @ f + + .align 5 + +/* * Interrupt dispatcher * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC */ @@ -1177,46 +1327,6 @@ .align 5 -/* - * Undef instr entry dispatcher - dispatches it to the correct handler for the processor mode - * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC - */ -vector_undefinstr: - @ - @ save mode specific registers - @ - ldr r13, .LCsund - str lr, [r13] @ save lr_UND - mrs lr, spsr - str lr, [r13, #4] @ save spsr_UND - @ - @ now branch to the relevent MODE handling routine - @ - mov r13, #I_BIT | MODE_SVC - msr spsr_c, r13 @ switch to SVC_32 mode - - and lr, lr, #15 - ldr lr, [pc, lr, lsl #2] - movs pc, lr @ Changes mode and branches - -.LCtab_und: .word __und_usr @ 0 (USR_26 / USR_32) - .word __und_invalid @ 1 (FIQ_26 / FIQ_32) - .word __und_invalid @ 2 (IRQ_26 / IRQ_32) - .word __und_svc @ 3 (SVC_26 / SVC_32) - .word __und_invalid @ 4 - .word __und_invalid @ 5 - .word __und_invalid @ 6 - .word __und_invalid @ 7 - .word __und_invalid @ 8 - .word __und_invalid @ 9 - .word __und_invalid @ a - .word __und_invalid @ b - .word __und_invalid @ c - .word __und_invalid @ d - .word __und_invalid @ e - .word __und_invalid @ f - - .align 5 /*============================================================================= * Undefined FIQs @@ -1228,8 +1338,49 @@ * other mode than FIQ... Ok you can switch to another mode, but you can't * get out of that mode without clobbering one register. */ +#ifndef CONFIG_ARCH_CX821XX vector_FIQ: disable_fiq subs pc, lr, #4 +#else +/******************************************************************************* +/ Function: vector_FIQ +/ Description: Handles fast interrupt exception, +/ +/ Inputs Working Outputs +/ R0 = NA R0 = R0 = Restored +/ R1 = NA R1 = R1 = Restored +/ R2 = NA R2 = R2 = Restored +/ R3 = NA R3 = R3 = Restored +/ R4 = NA R4 = R4 = Restored +/ R5 = NA R5 = R5 = Restored +/ R6 = NA R6 = R6 = Restored +/ R7 = NA R7 = R7 = Restored +/ R8 = NA R8 = R8 = Restored +/ R9 = NA R9 = R9 = Restored +/ R10 = NA R10 = R10 = Restored +/ R11 = NA R11 = R11 = Restored +/ R12 = NA R12 = R12 = Restored +/ +/ This routine is entered with r8-r14 (r8-r12, SP and LR) replaced by r8_fiq - +/ r14_fiq. The CPSR will have been copied to the SPSR_fiq. +/*******************************************************************************/ +vector_FIQ: + /* + Adjust return address in LR now since we we return via restoring all regs + including the LR, but the LR is restored to the PC (R15). + */ + sub lr, lr, #4 + + @ Save registers + stmfd sp!, {r0-r7, lr} + +#if 0 + @ call the FIQ handler + bl cnxt_do_FIQ +#endif + @ Restore registers and return (The "^" causes the CPSR to be restored from the SPSR) + ldmfd sp!, {r0-r7, pc}^ +#endif /*============================================================================= * Address exception handler @@ -1258,7 +1409,11 @@ .equ __real_stubs_start, .LCvectors + 0x200 .LCvectors: swi SYS_ERROR0 +#ifdef CONFIG_UCBOOTSTRAP /* The uCbootstrap system calls use */ + .word 0xe59ff038 /* an undefined instruction trap */ +#else b __real_stubs_start + (vector_undefinstr - __stubs_start) +#endif ldr pc, __real_stubs_start + (.LCvswi - __stubs_start) b __real_stubs_start + (vector_prefetch - __stubs_start) b __real_stubs_start + (vector_data - __stubs_start) diff -ur uClinux-2.4.6.0pre1/arch/armnommu/kernel/entry-common.S uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/entry-common.S --- uClinux-2.4.6.0pre1/arch/armnommu/kernel/entry-common.S 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/entry-common.S 2005-01-04 13:22:41.000000000 +0100 @@ -132,6 +132,10 @@ ldr ip, __cr_alignment ldr ip, [ip] mcr p15, 0, ip, c1, c0 @ update control register + /* NEW CODE */ + mov ip, #0 + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + /* NEW CODE */ #endif enable_irqs ip diff -ur uClinux-2.4.6.0pre1/arch/armnommu/kernel/entry-header.S uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/entry-header.S --- uClinux-2.4.6.0pre1/arch/armnommu/kernel/entry-header.S 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/entry-header.S 2005-01-04 18:56:21.000000000 +0100 @@ -131,6 +132,10 @@ ldr \rtemp, [\rbase, #OFF_CR_ALIGNMENT(\sym)] mcr p15, 0, \rtemp, c1, c0 + /* NEW CODE */ + mov \rtemp, #0 + mcr p15, 0, \rtemp, c7, c5, 0 @ invalidate I cache + /* NEW CODE */ #endif .endm diff -ur uClinux-2.4.6.0pre1/arch/armnommu/kernel/head-armv.S uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/head-armv.S --- uClinux-2.4.6.0pre1/arch/armnommu/kernel/head-armv.S 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/head-armv.S 2005-01-04 17:49:42.000000000 +0100 @@ -50,7 +50,8 @@ * containing both. */ .macro krnladr, rd, pgtable, rambase - bic \rd, \pgtable, #0x000ff000 + bic \rd, \pgtable, #0x00ff000 + bic \rd, \rd, #0x0300000 .endm /* @@ -123,16 +124,22 @@ orr r12, r12, #5 << 12 __entry: #endif -#if defined(CONFIG_ARCH_L7200) +/*----------------------------------------------------------------------------*/ /* * FIXME - No bootloader, so manually set 'r1' with our architecture number. */ + +#if defined(CONFIG_ARCH_L7200) mov r1, #MACH_TYPE_L7200 #elif defined(CONFIG_ARCH_INTEGRATOR) mov r1, #MACH_TYPE_INTEGRATOR #elif defined(CONFIG_ARCH_P52) mov r1, #MACH_TYPE_P52 +#elif defined(CONFIG_ARCH_CX821XX) + mov r1, #MACH_TYPE_CX821XX #endif + msr cpsr_c, # F_BIT | I_BIT | FIQ_MODE @ Put us in FIRQ mode and turn interrupts off + ldr r13, =_firq_stack_bottom @ initialize FIRQ stack ptr mov r0, #F_BIT | I_BIT | MODE_SVC @ make sure svc mode msr cpsr_c, r0 @ and all irqs disabled @@ -250,6 +257,7 @@ +/*====================== OUR PAGE TABLE SETUP ==========================*/ /* * Setup the initial page tables. We only setup the barest * amount which are required to get the kernel running, which @@ -293,15 +301,23 @@ * mapped region. We round TEXTADDR down to the * nearest megabyte boundary. */ - add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel - add r0, r0, #(TEXTADDR & 0x00f00000) >> 18 - str r3, [r0], #4 @ PAGE_OFFSET + 0MB + add r0, r4, #(0x8000000 & 0xff000000) >> 18 @ start of kernel + add r0, r0, #(0x8000000 & 0x00f00000) >> 18 + + mov r2, r0 + add r2, r2, #0x100 @ Load r2 with the last page table entry address + @ for 64Mb of SDRAM + +2: str r3, [r0], #4 @ PAGE_OFFSET + 0MB add r3, r3, #1 << 20 str r3, [r0], #4 @ PAGE_OFFSET + 1MB add r3, r3, #1 << 20 str r3, [r0], #4 @ PAGE_OFFSET + 2MB add r3, r3, #1 << 20 str r3, [r0], #4 @ PAGE_OFFSET + 3MB + add r3, r3, #1 << 20 + teq r0, r2 + bne 2b /* * Ensure that the first section of RAM is present. @@ -310,6 +326,7 @@ * 2. the kernel is executing in the same 256MB chunk * as the start of RAM. */ + mov r5, #0 bic r0, r0, #0x0ff00000 >> 18 @ round down and r2, r5, #0xf0000000 @ round down add r3, r8, r2 @ flags + rambase @@ -480,3 +497,9 @@ L_AT91_SF_CIDR: .long 0xfff00000 + .section .stack, "w" + +_firq_stack: +_firq_stack_top: + .space 512 +_firq_stack_bottom: diff -ur uClinux-2.4.6.0pre1/arch/armnommu/kernel/irq.c uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/irq.c --- uClinux-2.4.6.0pre1/arch/armnommu/kernel/irq.c 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/irq.c 2005-01-04 15:12:17.000000000 +0100 @@ -139,6 +139,7 @@ if (desc->lck_cnt > MAX_IRQ_CNT) { printk(KERN_ERR "IRQ LOCK: IRQ%d is locking the system, disabled\n", irq); disable_irq(irq); + desc->lck_cnt = 0; } } else { desc->lck_cnt = 0; @@ -156,74 +157,31 @@ struct irqaction * action; int cpu; - irq = fixup_irq(irq); - - /* - * Some hardware gives randomly wrong interrupts. Rather - * than crashing, do something sensible. - */ - if (irq >= NR_IRQS) - goto bad_irq; - desc = irq_desc + irq; - spin_lock(&irq_controller_lock); - desc->mask_ack(irq); - spin_unlock(&irq_controller_lock); - cpu = smp_processor_id(); irq_enter(cpu, irq); kstat.irqs[cpu][irq]++; desc->triggered = 1; - /* Return with this interrupt masked if no action */ action = desc->action; - if (action) { - int status = 0; - - if (desc->nomask) { - spin_lock(&irq_controller_lock); - desc->unmask(irq); - spin_unlock(&irq_controller_lock); - } - - if (!(action->flags & SA_INTERRUPT)) - __sti(); - - do { - status |= action->flags; - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - - if (status & SA_SAMPLE_RANDOM) - add_interrupt_randomness(irq); - __cli(); - - if (!desc->nomask && desc->enabled) { - spin_lock(&irq_controller_lock); - desc->unmask(irq); - spin_unlock(&irq_controller_lock); - } + if (action) + { + action->handler(irq, action->dev_id, regs); + } + else + { + spin_lock(&irq_controller_lock); + desc->mask(irq); + spin_unlock(&irq_controller_lock); } - - /* - * Debug measure - hopefully we can continue if an - * IRQ lockup problem occurs... - */ - check_irq_lock(desc, irq, regs); irq_exit(cpu, irq); if (softirq_pending(cpu)) do_softirq(); return; - -bad_irq: - irq_err_count += 1; - printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); - return; } #ifdef CONFIG_ARCH_ACORN diff -ur uClinux-2.4.6.0pre1/arch/armnommu/kernel/setup.c uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/setup.c --- uClinux-2.4.6.0pre1/arch/armnommu/kernel/setup.c 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/kernel/setup.c 2005-01-04 15:15:07.000000000 +0100 @@ -28,9 +28,7 @@ #include #include -#ifndef MEM_SIZE -#define MEM_SIZE (8*1024*1024) -#endif +#define MEM_SIZE DRAM_SIZE #ifndef CONFIG_CMDLINE #define CONFIG_CMDLINE "root=/dev/rom0" @@ -507,6 +505,10 @@ ROOT_DEV = MKDEV(0, 255); +#ifdef CONFIG_ARCH_CNXT + syshwinit(); +#endif + setup_processor(); mdesc = setup_architecture(machine_arch_type); machine_name = mdesc->name; @@ -567,8 +569,9 @@ NODE_DATA(0), memory_start >> PAGE_SHIFT, PAGE_OFFSET >> PAGE_SHIFT, - // 0x800000 >> PAGE_SHIFT, END_MEM >> PAGE_SHIFT); + + meminfo.end = END_MEM; /* Need for kcore size. OZH */ free_bootmem(memory_start, END_MEM - memory_start); reserve_bootmem(memory_start, bootmap_size); @@ -594,22 +597,26 @@ { char *p = buffer; - p += sprintf(p, "Processor\t: %s %s rev %d (%s)\n", - proc_info.manufacturer, proc_info.cpu_name, - (int)processor_id & 15, elf_platform); - - p += sprintf(p, "BogoMIPS\t: %lu.%02lu\n", - loops_per_jiffy / (500000/HZ), + p += sprintf(p, "\nProcessor\t: %s\n", proc_info.cpu_name); + p += sprintf(p, " manufacturer\t: %s\n", proc_info.manufacturer); +#ifdef CONFIG_CPU_ARM710 + p += sprintf(p, " core\t\t: arm7tdmi\n"); +#endif +#ifdef CONFIG_CPU_ARM940T + p += sprintf(p, " core\t\t: arm9tdmi\n"); +#endif +#ifdef CONFIG_CPU_32 + p += sprintf(p, " mode\t\t: 32 bit\n"); +#endif + p += sprintf(p, " format\t\t: "); + if ( ENDIANNESS == 'b') p += sprintf(p, "Big-Endial\n"); + else if ( ENDIANNESS == 'l') p += sprintf(p, "Little-Endian\n"); + else p += sprintf(p, "Unknow-Endian\n"); + p += sprintf(p, " bogomips\t: %lu.%02lu\n", + loops_per_jiffy / (500000/HZ), (loops_per_jiffy / (5000/HZ)) % 100); - p += sprintf(p, "Hardware\t: %s\n", machine_name); - - p += sprintf(p, "Revision\t: %04x\n", - system_rev); - - p += sprintf(p, "Serial\t\t: %08x%08x\n", - system_serial_high, - system_serial_low); + p += sprintf(p, "\nHardware\t: %s\n", machine_name); return p - buffer; } Only in uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/mm: discontig.c diff -ur uClinux-2.4.6.0pre1/arch/armnommu/mm/init.c uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/mm/init.c --- uClinux-2.4.6.0pre1/arch/armnommu/mm/init.c 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/mm/init.c 2005-01-04 15:17:51.000000000 +0100 @@ -591,10 +591,10 @@ num_physpages = 0; for (i = 0; i < meminfo.nr_banks; i++) { num_physpages += meminfo.bank[i].size >> PAGE_SHIFT; - printk(" %ldMB", meminfo.bank[i].size >> 20); + printk(" %ldK", meminfo.bank[i].size >> 10); } - printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT)); + printk(" = %luK total\n", num_physpages >> (10 - PAGE_SHIFT)); printk(KERN_NOTICE "Memory: %luKB available (%dK code, " "%dK data, %dK init)\n", (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), @@ -631,7 +631,7 @@ { if (!machine_is_integrator() && - !machine_is_p52() && - !machine_is_atmel()) { + !machine_is_atmel() && + !machine_is_cx821xx()) { free_area((unsigned long)(&__init_begin), (unsigned long)(&__init_end), "init"); diff -ur uClinux-2.4.6.0pre1/arch/armnommu/mm/proc-arm940.S uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/mm/proc-arm940.S --- uClinux-2.4.6.0pre1/arch/armnommu/mm/proc-arm940.S 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/mm/proc-arm940.S 2005-01-04 18:47:30.000000000 +0100 @@ -22,8 +22,8 @@ /* * the cache line size of the I and D cache */ -#define DCACHELINESIZE 32 -#define ICACHELINESIZE 32 +#define DCACHELINESIZE 16 +#define ICACHELINESIZE 16 /* * and the page size @@ -136,19 +136,21 @@ * Re-written to use Index Ops. * Uses registers r1, r3 and ip */ - mov r1, #7 << 5 @ 8 segments + mov r1, #4 << 4 @ 4 segments 1: orr r3, r1, #63 << 26 @ 64 entries 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index subs r3, r3, #1 << 26 bcs 2b @ entries 63 to 0 - subs r1, r1, #1 << 5 - bcs 1b @ segments 7 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 3 to 0 #endif teq r2, #0 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c10, 4 @ drain WB mov pc, lr +cpu_arm940_cache_clean_invalidate_all_string: + .asciz "cpu_arm940_cache_clean_invalidate_all\n" /* * cpu_arm940_cache_clean_invalidate_range(start, end, flags) * @@ -157,23 +159,13 @@ * start: Area start address * end: Area end address * flags: nonzero for I cache as well + * + * With ARM 940T, we cannot determine which lines are associated with which + * memory range. Therefore we clean and invalidate all. */ .align 5 ENTRY(cpu_arm940_cache_clean_invalidate_range) - bic r0, r0, #DCACHELINESIZE - 1 @ && added by PGM - sub r3, r1, r0 - cmp r3, #MAX_AREA_SIZE - bgt cpu_arm940_cache_clean_invalidate_all_r2 -1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry - add r0, r0, #DCACHELINESIZE - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry - add r0, r0, #DCACHELINESIZE - cmp r0, r1 - blt 1b - teq r2, #0 - movne r0, #0 - mcrne p15, 0, r0, c7, c5, 0 @ invalidate I cache - mov pc, lr + b cpu_arm940_cache_clean_invalidate_all_r2 /* * cpu_arm940_flush_ram_page(page) @@ -181,10 +173,14 @@ * clean and invalidate all cache lines associated with this area of memory * * page: page to clean and invalidate + * + * With ARM 940T, we cannot determine which lines are associated with which + * pages. Therefore we clean and invalidate all. */ .align 5 ENTRY(cpu_arm940_flush_ram_page) - mov pc, lr + sub r2, r2, r2 + b cpu_arm940_cache_clean_invalidate_all /* ================================ D-CACHE =============================== */ @@ -197,21 +193,16 @@ * around the boundaries if the start and/or end address are not cache * aligned. * + * With ARM 940T, we cannot determine which lines are associated with which + * pages. Therefore we clean and invalidate all. + * * start: virtual start address * end: virtual end address */ .align 5 ENTRY(cpu_arm940_dcache_invalidate_range) - tst r0, #DCACHELINESIZE - 1 - bic r0, r0, #DCACHELINESIZE - 1 - mcrne p15, 0, r0, c7, c10, 1 @ clean D entry - tst r1, #DCACHELINESIZE - 1 - mcrne p15, 0, r1, c7, c10, 1 @ clean D entry -1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry - add r0, r0, #DCACHELINESIZE - cmp r0, r1 - blt 1b - mov pc, lr + sub r2, r2, r2 + b cpu_arm940_cache_clean_invalidate_all /* * cpu_arm940_dcache_clean_range(start, end) @@ -220,26 +211,35 @@ * clean data, such that peripheral accesses to the physical RAM fetch * correct data. * + * With ARM 940T, we cannot determine which lines are associated with which + * range. Therefore we clean all DCache. + * * start: virtual start address * end: virtual end address */ .align 5 +cpu_arm940_dcache_clean_all: ENTRY(cpu_arm940_dcache_clean_range) - bic r0, r0, #DCACHELINESIZE - 1 - sub r1, r1, r0 - cmp r1, #MAX_AREA_SIZE - mov r2, #0 - bgt cpu_arm940_cache_clean_invalidate_all_r2 - -1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #DCACHELINESIZE - mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #DCACHELINESIZE - subs r1, r1, #2 * DCACHELINESIZE - bpl 1b - mcr p15, 0, r2, c7, c10, 4 @ drain WB + mov ip, #0 +#ifdef CONFIG_CPU_ARM940_FORCE_WRITE_THROUGH +#else +/* + * 'Clean whole DCache' + * Uses registers r1, r3 and ip + */ + mov r1, #4 << 4 @ 4 segments +1: orr r3, r1, #63 << 26 @ 64 entries +2: mcr p15, 0, r3, c7, c10, 2 @ clean D index + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 4 + bcs 1b @ segments 3 to 0 +#endif + mcr p15, 0, ip, c7, c10, 4 @ drain WB mov pc, lr +cpu_arm940_dcache_clean_all_string: + .asciz "cpu_arm940_dcache_clean_all\n" /* * cpu_arm940_dcache_clean_page(page) * @@ -248,23 +248,13 @@ * * page: virtual address of page to clean from dcache * - * Note: - * 1. we don't need to flush the write buffer in this case. - * 2. we don't invalidate the entries since when we write the page - * out to disk, the entries may get reloaded into the cache. + * With ARM 940T, we cannot determine which lines are associated with which + * page. Therefore we clean all DCache. + * */ .align 5 ENTRY(cpu_arm940_dcache_clean_page) -#ifndef CONFIG_CPU_ARM940_FORCE_WRITE_THROUGH - mov r1, #PAGESIZE -1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #DCACHELINESIZE - mcr p15, 0, r0, c7, c10, 1 @ clean D entry - add r0, r0, #DCACHELINESIZE - subs r1, r1, #2 * DCACHELINESIZE - bne 1b -#endif - mov pc, lr + b cpu_arm940_dcache_clean_all /* * cpu_arm940_dcache_clean_entry(addr) @@ -272,15 +262,14 @@ * Clean the specified entry of any caches such that the MMU * translation fetches will obtain correct data. * + * With ARM 940T, we cannot determine which lines are associated with which + * page. Therefore we clean all DCache. + * * addr: cache-unaligned virtual address */ .align 5 ENTRY(cpu_arm940_dcache_clean_entry) -#ifndef CONFIG_CPU_ARM940_FORCE_WRITE_THROUGH - mcr p15, 0, r0, c7, c10, 1 @ clean D entry -#endif - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mov pc, lr + b cpu_arm940_dcache_clean_all /* ================================ I-CACHE =============================== */ @@ -289,20 +278,18 @@ * * invalidate a range of virtual addresses from the Icache * + * With ARM 940T, we cannot determine which lines are associated with which + * page/range. Therefore we invalidate all ICache. Since this routine must + * also synchronize the I and D cache, we must flush the D cache + * * start: virtual start address * end: virtual end address */ .align 5 ENTRY(cpu_arm940_icache_invalidate_range) -1: mcr p15, 0, r0, c7, c10, 1 @ Clean D entry - add r0, r0, #DCACHELINESIZE - cmp r0, r1 - blo 1b - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 @ drain WB ENTRY(cpu_arm940_icache_invalidate_page) - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mov pc, lr + mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache + b cpu_arm940_dcache_clean_all /* ================================== TLB ================================= */ @@ -402,25 +389,6 @@ __arm940_setup: MRC p15, 0, R0, c1, c0, 0 @ get control register - -/* - * Clear out 'unwanted' bits (then put them in if we need them) - */ - bic r0, r0, #0x0e00 @ ....??r......... - bic r0, r0, #0x0002 @ ..............a. - bic r0, r0, #0x000c @ W,D - bic r0, r0, #0x1000 @ I -/* - * Turn on what we want - */ - orr r0, r0, #0x0001 @ Enable PU - -#ifdef CONFIG_CPU_ARM940_D_CACHE_ON - orr r0, r0, #0x0004 @ Enable D cache -#endif -#ifdef CONFIG_CPU_ARM940_I_CACHE_ON - orr r0, r0, #0x1000 @ I Cache on -#endif mov pc, lr .text diff -ur uClinux-2.4.6.0pre1/arch/armnommu/tools/mach-types uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/tools/mach-types --- uClinux-2.4.6.0pre1/arch/armnommu/tools/mach-types 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/tools/mach-types 2005-01-04 18:15:51.000000000 +0100 @@ -1,10 +1,11 @@ -# Database of machine macros and numbers +# +# This file is linux/arch/arm/tools/mach-types # # Please do not send patches to this file; it is automatically generated! # To add an entry into this database, please see Documentation/arm/README, # or contact rmk@arm.linux.org.uk # -# Last update: Fri Jan 19 10:49:57 2001 +# Last update: Tue Jul 29 14:17:26 2003 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -29,13 +30,13 @@ l7200 ARCH_L7200 L7200 19 pleb SA1100_PLEB PLEB 20 integrator ARCH_INTEGRATOR INTEGRATOR 21 -bitsy SA1100_BITSY BITSY 22 +h3600 SA1100_H3600 H3600 22 ixp1200 ARCH_IXP1200 IXP1200 23 p720t ARCH_P720T P720T 24 assabet SA1100_ASSABET ASSABET 25 victor SA1100_VICTOR VICTOR 26 lart SA1100_LART LART 27 -ranger ARCH_RANGER RANGER 28 +ranger SA1100_RANGER RANGER 28 graphicsclient SA1100_GRAPHICSCLIENT GRAPHICSCLIENT 29 xp860 SA1100_XP860 XP860 30 cerf SA1100_CERF CERF 31 @@ -48,7 +49,7 @@ netport SA1100_NETPORT NETPORT 38 pangolin SA1100_PANGOLIN PANGOLIN 39 yopy SA1100_YOPY YOPY 40 -coolidge SA1100_COOLIDGE coolidge 41 +coolidge SA1100_COOLIDGE COOLIDGE 41 huw_webpanel SA1100_HUW_WEBPANEL HUW_WEBPANEL 42 spotme ARCH_SPOTME SPOTME 43 freebird ARCH_FREEBIRD FREEBIRD 44 @@ -61,13 +62,304 @@ citygo SA1100_CITYGO CITYGO 51 pfs168 SA1100_PFS168 PFS168 52 spot SA1100_SPOT SPOT 53 -flexanet ARCH_FLEXANET FLEXANET 54 +flexanet SA1100_FLEXANET FLEXANET 54 webpal ARCH_WEBPAL WEBPAL 55 -dsc21 ARCH_DSC21 DSC21 56 -p52 ARCH_P52 P52 57 -spipe ARCH_SPIPE SPIPE 58 -atmel ARCH_ATMEL ATMEL 59 -uClinkII ARCH_UCLINKII UCLINKII 60 - -# The following are unallocated -empeg SA1100_EMPEG EMPEG +linpda SA1100_LINPDA LINPDA 56 +anakin ARCH_ANAKIN ANAKIN 57 +mvi SA1100_MVI MVI 58 +jupiter SA1100_JUPITER JUPITER 59 +psionw ARCH_PSIONW PSIONW 60 +aln SA1100_ALN ALN 61 +epxa ARCH_CAMELOT CAMELOT 62 +gds2200 SA1100_GDS2200 GDS2200 63 +psion_series7 SA1100_PSION_SERIES7 PSION_SERIES7 64 +xfile SA1100_XFILE XFILE 65 +accelent_ep9312 ARCH_ACCELENT_EP9312 ACCELENT_EP9312 66 +ic200 ARCH_IC200 IC200 67 +creditlart SA1100_CREDITLART CREDITLART 68 +htm SA1100_HTM HTM 69 +iq80310 ARCH_IQ80310 IQ80310 70 +freebot SA1100_FREEBOT FREEBOT 71 +entel ARCH_ENTEL ENTEL 72 +enp3510 ARCH_ENP3510 ENP3510 73 +trizeps SA1100_TRIZEPS TRIZEPS 74 +nesa SA1100_NESA NESA 75 +venus ARCH_VENUS VENUS 76 +tardis ARCH_TARDIS TARDIS 77 +mercury ARCH_MERCURY MERCURY 78 +empeg SA1100_EMPEG EMPEG 79 +adi_evb ARCH_I80200FCC I80200FCC 80 +itt_cpb SA1100_ITT_CPB ITT_CPB 81 +svc SA1100_SVC SVC 82 +alpha2 SA1100_ALPHA2 ALPHA2 84 +alpha1 SA1100_ALPHA1 ALPHA1 85 +netarm ARCH_NETARM NETARM 86 +simpad SA1100_SIMPAD SIMPAD 87 +pda1 ARCH_PDA1 PDA1 88 +lubbock ARCH_LUBBOCK LUBBOCK 89 +aniko ARCH_ANIKO ANIKO 90 +clep7212 ARCH_CLEP7212 CLEP7212 91 +cs89712 ARCH_CS89712 CS89712 92 +weararm SA1100_WEARARM WEARARM 93 +possio_px SA1100_POSSIO_PX POSSIO_PX 94 +sidearm SA1100_SIDEARM SIDEARM 95 +stork SA1100_STORK STORK 96 +shannon SA1100_SHANNON SHANNON 97 +ace ARCH_ACE ACE 98 +ballyarm SA1100_BALLYARM BALLYARM 99 +simputer SA1100_SIMPUTER SIMPUTER 100 +nexterm SA1100_NEXTERM NEXTERM 101 +sa1100_elf SA1100_SA1100_ELF SA1100_ELF 102 +gator SA1100_GATOR GATOR 103 +granite ARCH_GRANITE GRANITE 104 +consus SA1100_CONSUS CONSUS 105 +aaed2000 ARCH_AAED2000 AAED2000 106 +cdb89712 ARCH_CDB89712 CDB89712 107 +graphicsmaster SA1100_GRAPHICSMASTER GRAPHICSMASTER 108 +adsbitsy SA1100_ADSBITSY ADSBITSY 109 +pxa_idp ARCH_PXA_IDP PXA_IDP 110 +plce ARCH_PLCE PLCE 111 +pt_system3 SA1100_PT_SYSTEM3 PT_SYSTEM3 112 +murphy ARCH_MEDALB MEDALB 113 +eagle ARCH_EAGLE EAGLE 114 +dsc21 ARCH_DSC21 DSC21 115 +dsc24 ARCH_DSC24 DSC24 116 +ti5472 ARCH_TI5472 TI5472 117 +autcpu12 ARCH_AUTCPU12 AUTCPU12 118 +uengine ARCH_UENGINE UENGINE 119 +bluestem SA1100_BLUESTEM BLUESTEM 120 +xingu8 ARCH_XINGU8 XINGU8 121 +bushstb ARCH_BUSHSTB BUSHSTB 122 +epsilon1 SA1100_EPSILON1 EPSILON1 123 +balloon SA1100_BALLOON BALLOON 124 +puppy ARCH_PUPPY PUPPY 125 +elroy SA1100_ELROY ELROY 126 +gms720 ARCH_GMS720 GMS720 127 +s24x ARCH_S24X S24X 128 +jtel_clep7312 ARCH_JTEL_CLEP7312 JTEL_CLEP7312 129 +cx821xx ARCH_CX821XX CX821XX 130 +edb7312 ARCH_EDB7312 EDB7312 131 +bsa1110 SA1100_BSA1110 BSA1110 132 +powerpin ARCH_POWERPIN POWERPIN 133 +openarm ARCH_OPENARM OPENARM 134 +whitechapel SA1100_WHITECHAPEL WHITECHAPEL 135 +h3100 SA1100_H3100 H3100 136 +h3800 SA1100_H3800 H3800 137 +blue_v1 ARCH_BLUE_V1 BLUE_V1 138 +pxa_cerf ARCH_PXA_CERF PXA_CERF 139 +arm7tevb ARCH_ARM7TEVB ARM7TEVB 140 +d7400 SA1100_D7400 D7400 141 +piranha ARCH_PIRANHA PIRANHA 142 +sbcamelot SA1100_SBCAMELOT SBCAMELOT 143 +kings SA1100_KINGS KINGS 144 +smdk2400 ARCH_SMDK2400 SMDK2400 145 +collie SA1100_COLLIE COLLIE 146 +idr ARCH_IDR IDR 47 +badge4 SA1100_BADGE4 BADGE4 148 +webnet ARCH_WEBNET WEBNET 149 +d7300 SA1100_D7300 D7300 150 +cep SA1100_CEP CEP 151 +fortunet ARCH_FORTUNET FORTUNET 152 +vc547x ARCH_VC547X VC547X 153 +filewalker SA1100_FILEWALKER FILEWALKER 154 +netgateway SA1100_NETGATEWAY NETGATEWAY 155 +symbol2800 SA1100_SYMBOL2800 SYMBOL2800 156 +suns SA1100_SUNS SUNS 157 +frodo SA1100_FRODO FRODO 158 +ms301 SA1100_MACH_TYTE_MS301 MACH_TYTE_MS301 159 +mx1ads ARCH_MX1ADS MX1ADS 160 +h7201 ARCH_H7201 H7201 161 +h7202 ARCH_H7202 H7202 162 +amico ARCH_AMICO AMICO 163 +iam SA1100_IAM IAM 164 +tt530 SA1100_TT530 TT530 165 +sam2400 ARCH_SAM2400 SAM2400 166 +jornada56x SA1100_JORNADA56X JORNADA56X 167 +active SA1100_ACTIVE ACTIVE 168 +iq80321 ARCH_IQ80321 IQ80321 169 +wid SA1100_WID WID 170 +sabinal ARCH_SABINAL SABINAL 171 +ixp425_matacumbe ARCH_IXP425_MATACUMBE IXP425_MATACUMBE 172 +miniprint SA1100_MINIPRINT MINIPRINT 173 +adm510x ARCH_ADM510X ADM510X 174 +svs200 SA1100_SVS200 SVS200 175 +atg_tcu ARCH_ATG_TCU ATG_TCU 176 +jornada820 SA1100_JORNADA820 JORNADA820 177 +s3c44b0 ARCH_S3C44B0 S3C44B0 178 +margis2 ARCH_MARGIS2 MARGIS2 179 +ks8695 ARCH_KS8695 KS8695 180 +brh ARCH_BRH BRH 181 +s3c2410 ARCH_S3C2410 S3C2410 182 +possio_px30 ARCH_POSSIO_PX30 POSSIO_PX30 183 +s3c2800 ARCH_S3C2800 S3C2800 184 +fleetwood SA1100_FLEETWOOD FLEETWOOD 185 +omaha ARCH_OMAHA OMAHA 186 +ta7 ARCH_TA7 TA7 187 +nova SA1100_NOVA NOVA 188 +hmk ARCH_HMK HMK 189 +karo ARCH_KARO KARO 190 +fester SA1100_FESTER FESTER 191 +gpi ARCH_GPI GPI 192 +smdk2410 ARCH_SMDK2410 SMDK2410 193 +premium ARCH_PREMIUM PREMIUM 194 +nexio SA1100_NEXIO NEXIO 195 +bitbox SA1100_BITBOX BITBOX 196 +g200 SA1100_G200 G200 197 +gill SA1100_GILL GILL 198 +pxa_mercury ARCH_PXA_MERCURY PXA_MERCURY 199 +ceiva ARCH_CEIVA CEIVA 200 +fret SA1100_FRET FRET 201 +emailphone SA1100_EMAILPHONE EMAILPHONE 202 +h3900 ARCH_H3900 H3900 203 +pxa1 ARCH_PXA1 PXA1 204 +koan369 SA1100_KOAN369 KOAN369 205 +cogent ARCH_COGENT COGENT 206 +esl_simputer ARCH_ESL_SIMPUTER ESL_SIMPUTER 207 +esl_simputer_clr ARCH_ESL_SIMPUTER_CLR ESL_SIMPUTER_CLR 208 +esl_simputer_bw ARCH_ESL_SIMPUTER_BW ESL_SIMPUTER_BW 209 +hhp_cradle ARCH_HHP_CRADLE HHP_CRADLE 210 +he500 ARCH_HE500 HE500 211 +inhandelf2 SA1100_INHANDELF2 INHANDELF2 212 +inhandftip SA1100_INHANDFTIP INHANDFTIP 213 +dnp1110 SA1100_DNP1110 DNP1110 214 +pnp1110 SA1100_PNP1110 PNP1110 215 +csb226 ARCH_CSB226 CSB226 216 +arnold SA1100_ARNOLD ARNOLD 217 +psiboard SA1100_PSIBOARD PSIBOARD 218 +jz8028 ARCH_JZ8028 JZ8028 219 +h5400 ARCH_IPAQ3 IPAQ3 220 +forte SA1100_FORTE FORTE 221 +acam SA1100_ACAM ACAM 222 +abox SA1100_ABOX ABOX 223 +atmel ARCH_ATMEL ATMEL 224 +sitsang ARCH_SITSANG SITSANG 225 +cpu1110lcdnet SA1100_CPU1110LCDNET CPU1110LCDNET 226 +mpl_vcma9 ARCH_MPL_VCMA9 MPL_VCMA9 227 +opus_a1 ARCH_OPUS_A1 OPUS_A1 228 +daytona ARCH_DAYTONA DAYTONA 229 +killbear SA1100_KILLBEAR KILLBEAR 230 +yoho ARCH_YOHO YOHO 231 +jasper ARCH_JASPER JASPER 232 +dsc25 ARCH_DSC25 DSC25 233 +innovator ARCH_INNOVATOR INNOVATOR 234 +ramses ARCH_RAMSES RAMSES 235 +s28x ARCH_S28X S28X 236 +mport3 ARCH_MPORT3 MPORT3 237 +pxa_eagle250 ARCH_PXA_EAGLE250 PXA_EAGLE250 238 +pdb ARCH_PDB PDB 239 +blue_2g SA1100_BLUE_2G BLUE_2G 240 +bluearch SA1100_BLUEARCH BLUEARCH 241 +ixdp2400 ARCH_IXMB2400 IXMB2400 242 +ixdp2800 ARCH_IXMB2800 IXMB2800 243 +explorer SA1100_EXPLORER EXPLORER 244 +ixdp425 ARCH_IXDP425 IXDP425 245 +chimp ARCH_CHIMP CHIMP 246 +stork_nest ARCH_STORK_NEST STORK_NEST 247 +stork_egg ARCH_STORK_EGG STORK_EGG 248 +wismo SA1100_WISMO WISMO 249 +ezlinx ARCH_EZLINX EZLINX 250 +at91rm9200 ARCH_AT91 AT91 251 +orion ARCH_ORION ORION 252 +neptune ARCH_NEPTUNE NEPTUNE 253 +hackkit SA1100_HACKKIT HACKKIT 254 +pxa_wins30 ARCH_PXA_WINS30 PXA_WINS30 255 +lavinna SA1100_LAVINNA LAVINNA 256 +pxa_uengine ARCH_PXA_UENGINE PXA_UENGINE 257 +innokom ARCH_INNOKOM INNOKOM 258 +bms ARCH_BMS BMS 259 +ixcdp1100 ARCH_IXCDP1100 IXCDP1100 260 +prpmc1100 ARCH_PRPMC1100 PRPMC1100 261 +at91rm9200dk ARCH_AT91RM9200DK AT91RM9200DK 262 +armstick ARCH_ARMSTICK ARMSTICK 263 +armonie ARCH_ARMONIE ARMONIE 264 +mport1 ARCH_MPORT1 MPORT1 265 +s3c5410 ARCH_S3C5410 S3C5410 266 +zcp320a ARCH_ZCP320A ZCP320A 267 +i_box ARCH_I_BOX I_BOX 268 +stlc1502 ARCH_STLC1502 STLC1502 269 +siren ARCH_SIREN SIREN 270 +greenlake ARCH_GREENLAKE GREENLAKE 271 +argus ARCH_ARGUS ARGUS 272 +combadge SA1100_COMBADGE COMBADGE 273 +rokepxa ARCH_ROKEPXA ROKEPXA 274 +cintegrator ARCH_CINTEGRATOR CINTEGRATOR 275 +guidea07 ARCH_GUIDEA07 GUIDEA07 276 +tat257 ARCH_TAT257 TAT257 277 +igp2425 ARCH_IGP2425 IGP2425 278 +bluegrama ARCH_BLUEGRAMMA BLUEGRAMMA 279 +ipod ARCH_IPOD IPOD 280 +adsbitsyx ARCH_ADSBITSYX ADSBITSYX 281 +trizeps2 ARCH_TRIZEPS2 TRIZEPS2 282 +viper ARCH_VIPER VIPER 283 +adsbitsyplus SA1100_ADSBITSYPLUS ADSBITSYPLUS 284 +adsagc SA1100_ADSAGC ADSAGC 285 +stp7312 ARCH_STP7312 STP7312 286 +nx_phnx ARCH_PXA255 PXA255 287 +wep_ep250 ARCH_WEP_EP250 WEP_EP250 288 +inhandelf3 ARCH_INHANDELF3 INHANDELF3 289 +adi_coyote ARCH_ADI_COYOTE ADI_COYOTE 290 +iyonix ARCH_IYONIX IYONIX 291 +damicam1 ARCH_DAMICAM_SA1110 DAMICAM_SA1110 292 +meg03 ARCH_MEG03 MEG03 293 +pxa_whitechapel ARCH_PXA_WHITECHAPEL PXA_WHITECHAPEL 294 +nwsc ARCH_NWSC NWSC 295 +nwlarm ARCH_NWLARM NWLARM 296 +ixp425_mguard ARCH_IXP425_MGUARD IXP425_MGUARD 297 +pxa_netdcu4 ARCH_PXA_NETDCU4 PXA_NETDCU4 298 +ixdp2401 ARCH_IXDP2401 IXDP2401 299 +ixdp2801 ARCH_IXDP2801 IXDP2801 300 +zodiac ARCH_ZODIAC ZODIAC 301 +armmodul ARCH_ARMMODUL ARMMODUL 302 +ketop SA1100_KETOP KETOP 303 +av7200 ARCH_AV7200 AV7200 304 +arch_ti925 ARCH_ARCH_TI925 ARCH_TI925 305 +acq200 ARCH_ACQ200 ACQ200 306 +pt_dafit SA1100_PT_DAFIT PT_DAFIT 307 +ihba ARCH_IHBA IHBA 308 +quinque ARCH_QUINQUE QUINQUE 309 +nimbraone ARCH_NIMBRAONE NIMBRAONE 310 +nimbra29x ARCH_NIMBRA29X NIMBRA29X 311 +nimbra210 ARCH_NIMBRA210 NIMBRA210 312 +hhp_d95xx ARCH_HHP_D95XX HHP_D95XX 313 +labarm ARCH_LABARM LABARM 314 +m825xx ARCH_M825XX M825XX 315 +m7100 SA1100_M7100 M7100 316 +nipc2 ARCH_NIPC2 NIPC2 317 +fu7202 ARCH_FU7202 FU7202 318 +adsagx ARCH_ADSAGX ADSAGX 319 +pxa_pooh ARCH_PXA_POOH PXA_POOH 320 +bandon ARCH_BANDON BANDON 321 +pcm7210 ARCH_PCM7210 PCM7210 322 +nms9200 ARCH_NMS9200 NMS9200 323 +logodl ARCH_LOGODL LOGODL 324 +m7140 SA1100_M7140 M7140 325 +korebot ARCH_KOREBOT KOREBOT 326 +iq31244 ARCH_IQ31244 IQ31244 327 +koan393 SA1100_KOAN393 KOAN393 328 +inhandftip3 ARCH_INHANDFTIP3 INHANDFTIP3 329 +gonzo ARCH_GONZO GONZO 330 +bast ARCH_BAST BAST 331 +scanpass ARCH_SCANPASS SCANPASS 332 +ep7312_pooh ARCH_EP7312_POOH EP7312_POOH 333 +ta7s ARCH_TA7S TA7S 334 +ta7v ARCH_TA7V TA7V 335 +icarus SA1100_ICARUS ICARUS 336 +h1900 ARCH_H1900 H1900 337 +gemini SA1100_GEMINI GEMINI 338 +axim ARCH_AXIM AXIM 339 +audiotron ARCH_AUDIOTRON AUDIOTRON 340 +h2200 ARCH_H2200 H2200 341 +loox600 ARCH_LOOX600 LOOX600 342 +niop ARCH_NIOP NIOP 343 +dm310 ARCH_DM310 DM310 344 +seedpxa_c2 ARCH_SEEDPXA_C2 SEEDPXA_C2 345 +ixp4xx_mguardpci ARCH_IXP4XX_MGUARD_PCI IXP4XX_MGUARD_PCI 346 +h1940 ARCH_H1940 H1940 347 +scorpio ARCH_SCORPIO SCORPIO 348 +viva ARCH_VIVA VIVA 349 +pxa_xcard ARCH_PXA_XCARD PXA_XCARD 350 +csb335 ARCH_CSB335 CSB335 351 +ixrd425 ARCH_IXRD425 IXRD425 352 +iq80315 ARCH_IQ80315 IQ80315 353 +nmp7312 ARCH_NMP7312 NMP7312 354 +cx861xx ARCH_CX861XX CX861XX 355 diff -ur uClinux-2.4.6.0pre1/arch/armnommu/vmlinux-armv.lds.in uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/vmlinux-armv.lds.in --- uClinux-2.4.6.0pre1/arch/armnommu/vmlinux-armv.lds.in 2004-12-12 20:07:03.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/arch/armnommu/vmlinux-armv.lds.in 2005-01-04 15:21:17.000000000 +0100 @@ -2,6 +2,8 @@ * taken from the i386 version by Russell King * Written by Martin Mares */ + +INCLUDE arch/armnommu/mach-uClinkII/romfs.ld OUTPUT_ARCH(arm) ENTRY(stext) SECTIONS @@ -54,6 +56,10 @@ *(__ksymtab) __stop___ksymtab = .; + __start___kallsyms = .; /* All kernel symbols */ + *(__kallsyms) + __stop___kallsyms = .; + *(.got) /* Global offset table */ _etext = .; /* End of text section */ @@ -61,6 +67,8 @@ . = ALIGN(8192); + __data_start = .; + __data_rom_start = .; .data : { /* * first, the init task union, aligned @@ -80,9 +88,16 @@ *(.data) CONSTRUCTORS + . = ALIGN(32); /* To be sure to align .fs . OZH */ _edata = .; } + .fs : { + _romfs = ABSOLUTE (.); + . = . + romfs_size; + _end_romfs = ABSOLUTE (.); + } + .bss : { __bss_start = .; /* BSS */ *(.bss) diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/cpu-multi32.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/cpu-multi32.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/cpu-multi32.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/cpu-multi32.h 2005-01-04 13:22:41.000000000 +0100 @@ -154,6 +154,6 @@ #define cpu_set_pmd(pmdp, pmd) processor.pgtable.set_pmd(pmdp, pmd) #define cpu_set_pte(ptep, pte) processor.pgtable.set_pte(ptep, pte) -#define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys((unsigned long)(pgd))) +#define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys(pgd)) #endif diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/cpu-single.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/cpu-single.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/cpu-single.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/cpu-single.h 2005-01-04 13:22:41.000000000 +0100 @@ -84,6 +84,6 @@ extern void cpu_set_pte(pte_t *ptep, pte_t pte); extern volatile void cpu_reset(unsigned long addr); -#define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys((unsigned long)(pgd))) +#define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys(pgd)) #endif diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/io.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/io.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/io.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/io.h 2005-01-04 17:55:43.000000000 +0100 @@ -71,6 +71,14 @@ extern void insw(unsigned int port, void *from, int len); extern void insl(unsigned int port, void *from, int len); +extern void __raw_writesb(unsigned int addr, void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + #define outsb_p(port,from,len) outsb(port,from,len) #define outsw_p(port,from,len) outsw(port,from,len) #define outsl_p(port,from,len) outsl(port,from,len) diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/irq.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/irq.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/irq.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/irq.h 2005-01-04 13:22:41.000000000 +0100 @@ -8,7 +8,7 @@ #endif #ifndef NR_IRQS -#define NR_IRQS 128 +#define NR_IRQS 32 #endif /* diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/memory.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/memory.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/memory.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/memory.h 2005-01-04 13:22:41.000000000 +0100 @@ -22,20 +22,20 @@ * Virtual, bus and physical addresses are all the same when there's no MMU. * --gmcnutt */ -#define virt_to_bus(x) x -#define bus_to_virt(x) x -#define virt_to_phys(x) x -#define phys_to_virt(x) x +#define virt_to_bus(x) ((unsigned long) (x)) +#define bus_to_virt(x) ((void *) (x)) +#define virt_to_phys(x) ((unsigned long) (x)) +#define phys_to_virt(x) ((void *) (x)) /* * For some reason other asm/.h files refer to these instead of the more * public macros above. * --gmcnutt */ -#define __virt_to_bus(x) x -#define __bus_to_virt(x) x -#define __virt_to_phys(x) x -#define __phys_to_virt(x) x +#define __virt_to_bus(x) ((unsigned long) (x)) +#define __bus_to_virt(x) ((void *) (x)) +#define __virt_to_phys(x) ((unsigned long) (x)) +#define __phys_to_virt(x) ((void *) (x)) /* diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/module.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/module.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/module.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/module.h 2005-01-04 13:22:41.000000000 +0100 @@ -7,5 +7,6 @@ #define module_map(x) vmalloc(x) #define module_unmap(x) vfree(x) #define module_arch_init(x) (0) +#define arch_init_modules(x) do { } while (0) #endif /* _ASM_ARM_MODULE_H */ diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/page.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/page.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/page.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/page.h 2005-01-04 15:22:28.000000000 +0100 @@ -1,6 +1,8 @@ #ifndef _ASMARM_PAGE_H #define _ASMARM_PAGE_H +#include +#include #include #define PAGE_SIZE (1UL << PAGE_SHIFT) @@ -91,11 +93,9 @@ #endif /* !__ASSEMBLY__ */ -#include -#include -#define __pa(x) __virt_to_phys((unsigned long)(x)) -#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) +#define __pa(x) __virt_to_phys(x) +#define __va(x) __phys_to_virt(x) #ifndef CONFIG_DISCONTIGMEM diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/proc-armv/uaccess.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/proc-armv/uaccess.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/proc-armv/uaccess.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/proc-armv/uaccess.h 2005-01-04 13:22:41.000000000 +0100 @@ -37,7 +37,7 @@ #include #ifdef CONFIG_UCLINUX #define __range_ok(addr,size) 0 -#define __addr_ok(addr) 0 +#define __addr_ok(addr) 1 #else /* We use 33-bit arithmetic here... */ diff -ur uClinux-2.4.6.0pre1/include/asm-armnommu/virtconvert.h uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/virtconvert.h --- uClinux-2.4.6.0pre1/include/asm-armnommu/virtconvert.h 2004-12-12 20:07:05.000000000 +0100 +++ uClinux-2.4.6.0pre0.actiontecorig/include/asm-armnommu/virtconvert.h 2005-01-04 15:23:33.000000000 +0100 @@ -9,7 +9,6 @@ #define mm_vtop(vaddr) ((unsigned long) vaddr) -#define mm_vtop(vaddr) ((unsigned long) vaddr) #endif #endif